1. Field of the Invention
The present invention generally relates to determining when to generate interrupt signals, between a host processor and a peripheral device. For example, the peripheral device may be a transmit device.
2. Background Art
A transmit portion of a digital communications system typically supports the transmission of different types of information having differing Quality-of-Service (QoS) requirements. Exemplary information types could include encoded voice, digital video, or Internet Protocol (IP) data. In the case of Asynchronous Transfer Mode (ATM) systems, data to be transmitted is typically stored until ready for transmission in a set of queues. In ATM systems, the storage of data in a queue is often determined based on its destination and/or priority, called “per-Virtual Circuit (VC) priority queuing.” Data stored in each of the queues is then transmitted at its appropriately scheduled time, which is determined based on the QoS requirements of the VC.
When implementing a transmit apparatus with multiple transmit queues, it is necessary for the host controller of the apparatus to monitor the full and empty state of each host controller queue. It is the responsibility of the host controller to release data storage buffers submitted to the host controller queue once the data associated with the buffer has been transmitted from the transmitter device queue. Typical implementations of this require the host controller to periodically poll the status of the transmit device queue or receive an interrupt from the transmit device once related host controller storage buffer data has been transmitted from the transmit device queue. Periodic polling of transmit device queue status can result in an unnecessary amount of software overhead. Also, excessive interrupt servicing can result in a slowdown of system performance.
Therefore, what is needed is a system and a method that can reduce the overhead in a host controller caused by polling of the transmit device queue and that can reduce the time spent servicing interrupt signals in the host controller.